As the device densities of integrated circuits continue to increase, the metallurgy technologies utilized to interconnect individual devices must meet more stringent requirements. For one, higher device counts necessitate multiple levels of metallurgy. As the number of metal layers increases, it is important that the insulator layers separating these metal layers be as planar as possible. If planarity is not maintained, the resulting severe topologies may cause metal opens or shorts.
Another constraint placed upon state-of-the-art metallurgy technologies is that the vias utilized to interconnect the metal layers must be formed in as small a space as possible. This is commonly accomplished by anisotropically patterning the insulator (e.g., by reactive ion etching (RIE) in a fluorine-based gaseous plasma) to form vias having vertical sidewalls.
Yet another constraint is the minimization of contact resistance. Because of the sheer number of devices to be connected at the first level of metal, the resistive load on (and hence the signal delays associated with) this metal level will increase. Interconnect materials that minimize contact resistance will decrease loading. Refractory metals such as tungsten have been shown to possess the requisite resistivity properties. Moreover, because CVD tungsten can be conformally deposited to fill vertical-walled vias formed in an insulator layer, the previously-mentioned via density constraint can also be met by the adoption of CVD tungsten as the interconnect material.
Prior art approaches have attempted to provide a planarized insulating layer having planarized studs imbedded therein. U.S. Pat. No. 4,470,874, entitled "Planarization of Multi-Level Interconnected Metallization System" (issued Sept. 11, 1984, to Bartush et al and assigned to the assignee of the present invention) discloses a process wherein aluminum-based studs are formed on a substrate, a glass passivation layer is deposited to cover the stud, a planarizing photoresist layer is deposited on the passivation layer, the photoresist layer is exposed to an etchant that removes the photoresist layer and the glass passivation layer at substantially the same rate, and residual amounts of the glass passivation layer are removed in an etchant that attacks the previously-formed interconnect studs and the glass passivation layer at substantially the same rate. Note that this latter etchant, is disclosed as being an argon-based sputter etch, an ion milling step or a polishing step.
U.S. Pat. No. 4,614,021, entitled "Pillar Via Process" (issued Sept. 30, 1986, to Hulseweh et al and assigned to Motorola) discloses a process wherein a first level of metal is defined on a substrate, interconnecting stud structures are defined on the first metal layer, a thick passivation layer is deposited to cover the conductive studs, a planarizing resist layer is coated on the dielectric layer, and the resist layer is exposed to an etchant that removes the resist and the passivation layer at substantially the same rate so as to planarize the passivation layer.
In the prior art it is also known to coat a dielectric layer on a substrate, defined vias in the dielectric layer, fill the vias with metal, coat the structure with a planarizing resin layer, and expose the resin layer to an etchant that removes the resin as well as portions of the metal layer outside the vias at substantially the same rate. Such processes are disclosed in U.S. Pat. No. 4,520,041, entitled "Method for Forming Metallization Structure Having Flat Surface on Semiconductor Substrate" (issued May 28, 1985, to Aoyama et al and assigned to Toshiba) and U.S. Pat. No. 4,614,563, entitled "Process for Producing Multi-Layer Conductor Structure" (issued Sept. 30, 1986, to Kubo and assigned to Fuji Photo Film Company). In both processes, a metal:resin etch rate ratio of 1:1 must be maintained in order to provide a planar surface. Moreover, note that in both patents the portions of the metal laying outside the vias are disposed on a relatively planar passivation layer.
As shown in FIG. 3 of the above-mentioned co-pending U.S. Patent Application Ser. No. 791,860, another planarization method consists of planarizing the passivation layer prior to via definition, and then overfilling the subsequently-formed vias with metal. Portions of the metal lying outside the vias are then removed by polishing. More specifically, the application discloses (at Table 1) a plurality of acidic chem-mech slurries that maximize the polishing rate of aluminum relative to silicon oxide.
The present inventors investigated the possibility of planarizing the passivation film after via definition and prior to metal deposition. If vias are defined in a pre-planarized passivation layer, the underlying topography will produce vias of grossly varying depths. If the etch process is continued so as to fully define the deepest vias, the more shallow vias will be greatly overetched and the underlying structures may be substantially eroded. At the same time, because of the abovementioned vertical via and contact resistance constraints, the inventors wanted to utilize a conformal metal as the via-filling metallurgy. However, none of the above-mentioned prior art techniques specifically address simultaneously planarizing a via-filling metal and a non-planar insulator layer so as to form a planarized metal-insulator surface.